1. Field of the Invention
This invention relates to an active matrix liquid crystal display, and more particularly to an active matrix liquid crystal display wherein it is provided with a device for applying a gate pulse to transistors connected to picture elements (or pixels) consisting of liquid crystals.
2. Description of the Prior Art
The conventional active matrix liquid crystal display device displays a picture by controlling the light transmissivity of liquid crystal using an electric field. As shown in FIG. 1, such a liquid crystal display device includes a data driver 12 for driving signal lines SL1 to SLm at a liquid crystal panel 10, and a gate driver 14 for driving gate lines GL1 to GLn at a liquid crystal panel 10. In the liquid crystal panel 10, pixels 11 connected to signal lines SL and gate lines GL are arranged in an active matrix pattern. Each pixel 11 includes a liquid crystal cell Clc for responding to a data voltage signal DVS from the signal line SL to control a transmitted light quantity, and a thin film transistor (TFT) CMN for responding to a scanning signal SCS from the gate line GL to switch the data voltage signal DVS to be applied from the signal line SL to the liquid crystal cell Clc. As the gate lines GL1 to GLn are sequentially driven, the data driver 12 applies the data voltage signal DVS to all the signal lines SL1 to SLm. The gate driver 14 allows the gate lines GL1 to GLn to be sequentially enabled for each horizontal synchronous interval by applying the scanning signal SCS to the gate lines GL1 to GLn sequentially. To this end, the liquid crystal display device includes a shift register 16 responding to a gate start pulse from a control line CL and a gate scanning clock GSC from a gate clock line GCL, and a level shifter 18 connected between the shift register 16 and the gate lines GL1 to GLn. The shift register 16 outputs the gate start pulse GSC from the control line CL to one of n output terminals QT1 to GTn and, at the same time, responds to the gate scanning clock GSC to shift the gate start pulse GSP from the first output terminal QT1 to the nth output terminal QTn sequentially. The level shifter 18 generates n scanning signals SCS by shifting voltage levels of the output signals of the shift register 16. To this end, the level shifter 18 consists of n inverters 19 that are connected between the n output terminals QT1 to QTn of the shift register 16 and the n gate lines GL respectively, and are fed with low and high level gate voltages Vgl and Vgh in a direct current shape from first and second voltage line FVL and SVL respectively. The inverters 19 selectively supply any one of the low and high level gate voltages Vgl and Vgh to the gate line GL in accordance with a logical state at the output terminal QT of the shift register 16. Accordingly, only one of the n scanning signals SCS has the high-level gate voltage Vgh. In this case, the TFT CMN receiving a scanning signal SCS having the high level gate voltage Vgh from the gate line GL is turned on and the liquid crystal cell Clc charges the data voltage signal DVS during an interval when the TFT CMN is turned on. The voltage charged into the liquid crystal cell Clc in this manner drops when the TFT CMN is turned off and therefore becomes lower than the voltage of the data voltage signal DVS. Accordingly, a feed through voltage ΔVp corresponding to a difference voltage between the voltage charged in the liquid crystal cell and the data voltage signal DVS is generated. This feed through voltage ΔVp is caused by a parasitic capacitance existing between the gate terminal of the TFT CMN and the liquid crystal cell Clc and which changes a transmitted light quantity at the liquid crystal cell Clc periodically. As a result, a flicker and a residual image are generated in the picture displayed on the liquid crystal panel.
In order to suppress such a feed through voltage ΔVp, as shown in FIG. 1, support capacitors Cst are connected, in parallel, to the liquid crystal cells. The support capacitor Cst compensates for the liquid crystal cell voltage when the TFT CMN is turned off, thereby suppressing the feed through voltage ΔVp as expressed in the following formula:
                              Δ          ⁢          Vp                =                                            (                              Von                -                Voff                            )                        ·            Cgs                                Clc            +            Cst            +            Cgs                                              (        1        )            in which Von represents a voltage at the gate line GL upon turning-on of the TFT CMS; Voff represents the voltage at the gate line GL upon turning-off of the TFT CMS; and Cgs represents the capacitance value of a parasitic capacitor existing between the gate terminal of the TFT CMN and the liquid crystal cell. As seen from the formula (1), the feed through voltage ΔVp increases depending on a voltage difference at the gate line GL upon turning-on and turning off of the TFT CMN. In order to suppress the feed through voltage ΔVp sufficiently, the capacitance value of the support capacitor CSt must be increased. This causes apertures of pixels to be increased, so that it is impossible to obtain a sufficient display contrast. As a result, it is difficult to suppress the feed through voltage ΔVp sufficiently by means of the support capacitor Cst.
As another alternative for suppressing the feed through voltage ΔVp, there has been suggested a liquid crystal display device adopting a scanning signal control system for allowing the falling edge of the scanning signal SCS to have a gentle slope. In the liquid crystal display device of scanning signal control system, the falling edge of the scanning signal SCS changes in the shape of a linear function as shown in FIG. 2A, an exponential function as shown in FIG. 2B, or a ramp function as shown in FIG. 2C. Examples of such a liquid crystal display device of scanning signal control system are disclosed in the Japanese Patent Laid-open Gazette Nos. 1994-110035 and 1997-258174 and the U.S. Pat. No. 5,587,722. However, these liquid crystal display devices of scanning signal control system additionally require circuit modification of the gate driver or a new waveform modifying circuit to be positioned between the gate driver and each gate line at the liquid crystal panel.
For example, as shown in FIG. 3, the liquid crystal display device of the scanning signal control system disclosed in the Japanese Patent Laid-open Gazette No. 1994-110035 includes an integrator 22 connected between a scanning driver cell 20 and a gate line GL. The integrator 22 consists of a resistor R1 between the scanning driver cell 20 and the gate line GL, and a capacitor C1 connected between the gate line GL and the ground voltage line GVL. The integrator 22 integrates a scanning signal SCS to be applied from the gate driver cell 20 to the gate line GL, thereby changing the falling edge of the scanning signal SCS into the shape of an exponential function. A TFT CMN included in a pixel 11 is turned on until a voltage of the scanning signal SCS from the gate line GL drops less than its threshold voltage. Although electric charges charged in a liquid crystal cell Clc are pumped into the gate line GL, sufficient electric charges are charged into the liquid crystal cell Clc by a data voltage signal DVS passing through the TFT CMN from a signal line SL. Therefore, the voltage charged in the liquid crystal cell Clc does not drop. When a voltage of the scanning signal SCS on the gate line GL drops down under the threshold voltage of the TFT CMN, the voltage variation swing is less than the threshold voltage of the TFT CMN. Thus, an electric charge amount pumped from the liquid crystal cell Clc into the gate line GL becomes very small. As a result, the feed through voltage ΔVp can be suppressed sufficiently.
In the liquid crystal display device of the scanning signal control system as described above, the feed through voltage ΔVp is sufficiently suppressed to reduce flickering and residual images considerably but since a waveform modifying circuit such as an integrator for each gate line must be added, the circuit configuration thereof becomes very complex. Further, because the rising edge of the scanning signal also changes slowly due to the waveform modifying circuit, the charge initiation time at the liquid crystal cell is delayed.
Meanwhile, the U.S. Pat. No. 5,587,722 discloses a shift register selectively receiving power supply voltages VVDD and VVDD·R1/(R1+R2), as shown in FIG. 18. The shift register responds to the power supply voltages VVDD and VVDD·R1/(R1+R2) and generates a stepwise pulse. However, the shift register must be driven at a high voltage because the power supply voltage VVDD is equal to a high-level gate voltage to be applied to gate lines on the liquid crystal display panel. In the other word, inverters included in the shift register operate at about 25 V of the driving voltage. Due this end, the active matrix liquid crystal display device disclosed in U.S. Pat. No. 5,587,722 consumes a large amount of power.